SHARC

Harvard Architecture is a generic term for a microprocessor architecture which is able to access two blocks of memory simultaneously; these blocks are used to hold program code and data. Normal CPUs only have a single data bus, and can therefore only access one memory location at a time, although the use of caches reduces this difficulty in more sophisticated processors. By dividing memory into 2 separate blocks, one for data and one for the program, a Harvard Architecture CPU can access blocks both at the same time, the main cost being that the division between the two blocks is fixed.

Analog Devices' Super Harvard Architecture is a development of this. Memory is divided into 2 separate blocks, which can be accessed simultaneously, but each block can be divided freely between program and data: thus data in both blocks can be accessed simultaneously, or program in one and data in the other. However, this on its own is not terribly impressive: many other DSPs separate program from data memory, and some, even quite primitive chips such as the Oak, are able to access two blocks of data memory and one of program memory simultaneously.

The Analog Devices SHARC chips do have a number of other features that make them attractive: they possess a limited parallelism, able to perform certain combinations of instructions at the same time, although the claimed performance figures of 120 MIPS with a 40 MHz processor will never be realised in real-world applications. Added to this, they have a pipelined architecture with conditional execution and delayed branch instructions that reduce the bad effects of branching. They use 48-bit program memory to give near-VLIW instruction size, and can also use this for a 40-bit floating point format.

They also have full 32-bit floating point arithmetic, and highly efficient libraries for common DSP applications like Fourier Transforms and FIR filters. They are able to do SIMD (Single Instruction Multiple Data) instructions on 2 consecutive memory locations, with restrictions. They also have such common DSP features as no-overhead loops and can perform single-cycle MAC (Multiply-Accumulate) operations. Added to this, there is hardware support for A-law and mu-law companding, used for speech compression.

The chips also have a sophisticated DMA controller, able of arbitrating between a number of different Direct Memory Access operations, including communicating between internal and external memory and peripherals running at different speeds. The chips contain varying amounts of RAM, which are big enough to house many DSP applications.

They possess a variety of communication ports as well, most SHARC chips having a combination of SPORTs, short for Serial Ports, which are bi-directional serial connections, and the link ports, which are 4-bit parallel ports designed for communication between SHARCs. One of the main attractions of the SHARC for developers is the ability to connect a number of cheap DSPs to perform more complex tasks.

For development, they come with a C and C++ compiler, although this has not been without its bugs; in the first version of Visual DSP++ the interrupt handlers in C/C++ did not work at all, though this has since been corrected. They also have a powerful debugger able to simulate chip function and interact with an ICE or In-Circuit Emulator via a JTAG interface. (We had problems with this crashing repeatedly but were unsure if it was a fault in our hardware.)

They have an interesting assembler with a rather unusual syntax. Instead of saying "ADD r1, r2, r3", the assembler uses instructions of the form "r3 = r1 + r2". This solves the annoying problem of remembering the order of operands in MOV statements, and makes the C programmer feel more at home, which is lucky, because it is hard or impossible to produce efficient code in C. As an example, we found extremely highly optimised C code (a prime candidate for the Obfuscated C Contest) when re-written in assembler ran about 2.5 times faster. Although the inline assembler support is good, there are few features enabling the DSP features to be accessed from C.

SHARCs are widely used in audio processing applications, such as mp3 encoding and decoding. However, their computational power is meagre compared to Texas Instruments' range of DSP chips, and TI chips like the C54 tend to be preferred for low-power applications such as mobile phones. The rise in special-purpose system-on-chip solutions has also threatened the general purpose DSP market.

For this reason, Analog Devices has introduced the TigerSHARC range of chips, which come closer to TI's performance, and have been working with Intel on BlackFin, a new DSP architecture. Though they are less powerful than some chips now around, the SHARC DSPs still offer a cheap solution, are by now well-tested and well-supported, and have many useful capabilities for interfacing and signal processing applications. I'd still rather have a TI C67X, though.