A
Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a popular type of transistor, commonly used in
CMOS logic on
ICs and as (largely)
electrically isolated switches/
drivers which are
often refered to as
power MOSFETs. MOSFETs are a type of
Insulated Gate
Field Effect Transistor (
IGFET).
A given MOSFET has 2 primary characteristics that dictate its behavior: it is either PMOS or NMOS, and either enhancement mode, or depletion mode.
Enhancement mode devices tend to be more common, but PMOS and NMOS devices are often present in similar numbers in
Complementary Metal-Oxide-Semiconductor (CMOS) devices (this is what the complementary portion stands for).
Circuit Symbols
Enhancement Mode Depletion Mode
| | | |
||---+ D ||---+ S ||---+ D ||---+ S
| | | || || |
G --||<--+ B G --||-->+ B G --||<--+ B G --||-->+ B
| | | || | ||
||---+ S ||---+ D ||---+ S ||---+ D
| | | |
Simplified (Current) Symbols:
| | | |
|---+ D |<--+ S ||---+ D ||<--+ S
G --|| G --|| G --||| G --|||
|-->+ S |---+ D ||-->+ S ||---+ D
| | | |
NMOS PMOS
Logic (CMOS) Symbols:
| |
|--+ |--+
G -|| G -o||
|--+ |--+
| |
NMOS PMOS
Here, G indicates the gate of the transistor, which controls current flow
between S, the source of majority carriers and D, the drain. B indicates
a body connection.
Basic Operation
An NMOS Enhancement Mode MOSFET Trivial Circuit
Gate Vdd
| ___
Source | Drain |
+------+ | +------- |
| | MMMMMMMM+MMMMMMM | |---+
| | OOOOOOOOOOOOOOOO | +---||
| +-NN+NN-------------------NN+NN-+ | |-->+
| | NNNNN -channel- NNNNN | | |
| | NNNNN NNNNN | + | | ^
| | | Vg (V) | | I
| | | - | | |
| | Body (P) | +--------+
| +---------------+---------------+ |
| | ---
---+------------------+ /// Vss
N = N-type material
P = P-type material
O = Oxide (insulator) layer
M = Metal/Polysilicon layer
-
For the NMOS device pictured, connected as in the "trivial circuit", assume
that Vg, the Gate voltage, equals 0. In this case, the Gate voltage is
the same as the Source and Body voltage, also grounded (connected to Vss). That is:
Vg = Vs
The
majority carrier in an NMOS device is the electron, possessing negative
charge, and which can move freely through N-type material, but not through
P-type material. In this situation, since the channel is composed of P-type
body material, no current is allowed to flow (I = 0), and the device is
off.
-
Now, suppose that Vg is increased past some level Vtn,
which is called the threshold voltage (Vtn might be 1V). That is:
Vg - Vtn > Vs
Once the gate voltage has risen past this level, some of the negative
charge carriers from the source and drain are attracted to the gate,
effectively creating a
channel of N-type material between the Source and Drain. Now, a negative
(electron) current is
able to flow through the channel from the source to the (higher voltage) drain: the transistor turns
on.
I < 0
-
Now, the fact that there is a potential difference between the Drain and
the Source means that the potential difference through the channel near the
source side (Vg-Vs)
is greater than the potential difference through the channel near the drain
side (Vg - Vd, where Vd > Vs, thus
Vg - Vd < Vg - Vs). This means
that the channel is not as "deep" near the drain as near the source:
Gate
|
Source | Drain
+------+ | +-------
| | MMMMMMMM+MMMMMMM |
| | OOOOOOOOOOOOOOOO |
| +-NN+NNNNNNNNNNNNNNNNNNNNNNN+NN-+
| | NNNNNNNNNNNNNNNNNN NNNNN |
| | NNNNN channel NNNNN |
| | |
| | |
| | Body (P) |
| +---------------+---------------+
| |
---+------------------+
In fact, the current through the channel is controlled by this potential
difference, according to the following equation:
I =
-(1/2)*(K'n)*(W/L)*(2*(Vg - Vtn - Vs)*(Vd - Vs) - (Vd - Vs)2)
(NMOS Ohmic Region)
Where, K'n is the process parameter, the product of carrier
mobility and gate capacitance, and (W/L) is the aspect ratio. (Typically,
the aspect ratio can be modified by the designer of a CMOS Integrated
circuit, while the process parameter cannot.)
If the drain voltage exceeds the Gate voltage by a large enough amount,
the channel depth will drop to zero, and the channel will be in
pinch-off. This occurs when Vg - Vtn <
Vd. At this point, the device is said to be in Saturation, and no
further increase the the Drain voltage will result in an increase in current.
Thus, the current through the device is controlled solely by the Gate voltage,
and the following equation applies:
I =
-(1/2)*(K'n)*(W/L)*(Vg - Vtn -
Vs)2 (NMOS Saturation Region)
PMOS devices operate analogously, except that the Gate voltage must be
lower than the source voltage, and the source, drain, and
channel are P-type material, while the body is N-type. Of course, the
charge carrier in a PMOS transistor is not the electron, but the
positively charged hole.
Depletion mode devices are different, in that, instead of
creating (i.e. enhancing) a channel, the channel is already pre-existing, and
one uses the gate to deplete the channel, cutting off current.